1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory. In particular, the present invention relates to an electrically writable and erasable semiconductor nonvolatile memory (also referred to as the xe2x80x9cEEPROMxe2x80x9d or xe2x80x9celectrically erasable and programmable read only memoryxe2x80x9d). Also, the present invention relates to a semiconductor device which has the semiconductor nonvolatile memory.
It should be noted here that the term xe2x80x9celectrically writable and erasable semiconductor nonvolatile memory (EEPROM)xe2x80x9d refers to a whole of semiconductor nonvolatile memories that are electrically writable and electrically erasable, and examples thereof include an EEPROM that is capable of performing erasing on a bit-by-bit basis and a flash memory. Also, unless being specified, the terms xe2x80x9cnonvolatile memoryxe2x80x9d and xe2x80x9csemiconductor nonvolatile memoryxe2x80x9d are used as synonyms for the term xe2x80x9cEEPROMxe2x80x9d. Also, the term xe2x80x9csemiconductor devicexe2x80x9d refers to a whole of devices that function by utilizing semiconductor characteristics. Examples of the semiconductor device include a microprocessor, electrooptical devices such as a liquid crystal display device and a light-emitting device, and an electronic equipment in which there is installed a microprocessor or an electrooptical device.
2. Related Background Art
In recent years, an electrically writable and erasable semiconductor nonvolatile memory (EEPROM) (in particular, a flash memory) has drawn attention as a strong candidate for a memory that will replace a magnetic disk or a DRAM. In particular, a so-called multilevel nonvolatile memory, in which each memory element stores multi-state data more than binary data, receives attention as a mass storage memory.
In the EEPROM, there are usually performed verify writing or verify erasing that includes an operation for confirming that a state after writing or erasing exists within a predetermined range. In particular, in a multilevel nonvolatile memory, it is required to control the state after writing or erasing with high precision, therefore such a verify operation becomes indispensable.
In a conventional verify writing/erasing operation, an operation period for performing writing/erasing for a certain period, and a reading period for confirming that the state after writing/erasing exists within a predetermined range, are alternately performed.
A manner in which the operation period and the reading period are alternately performed will be described with reference to FIGS. 2 and 3. FIG. 2 is a simplified block diagram in which a reading circuit 202 and writing/erasing circuit 201 are connected to a selected memory cell 203. A verify signal Sv is outputted from the reading circuit 202 and is inputted into the writing/erasing circuit 201. The writing/erasing circuit 201 performs writing/erasing by referring to the verify signal Sv. A procedure for verify writing/erasing is shown in FIG. 3. In FIG. 3, the reading circuit first operates (denoted as xe2x80x9cactivexe2x80x9d) to perform reading. During this operation, the writing/erasing circuit does not operate (denote xe2x80x9cnot activexe2x80x9d). The verify signal Sv outputted from the reading circuit becomes xe2x80x9cLowxe2x80x9d in the case where a read state of the memory cell differs from a target state. On the other hand, the verify signal Sv becomes xe2x80x9cHighxe2x80x9d in the case where the read state of the memory cell coincides with the target state. In the case where the verify signal Sv is Low, the writing/erasing circuit starts its operation (becomes xe2x80x9cactivexe2x80x9d) after the reading operation is finished, to perform writing/erasing for a certain period. Following this, reading is performed again and the state of the memory cell is compared with the target state. Then, in a like manner, if the verify signal Sv remains Low, writing/erasing is performed again for a certain period. At a point when the verify signal Sv becomes High after repeating these operations, the verify writing/erasing is finished. The conventional verify operation is performed in this manner.
The verify operation described above is an extremely effective means as a method of controlling the threshold voltage of a memory element with high precision. In particular, in the case of a multilevel nonvolatile memory that requires a narrow distribution width of the threshold voltage or in the case where the increases of variations are unavoidable due to the miniaturization, the verify operation is indispensable. However, the conventional verify operation necessitates the repetition of writing/erasing and reading, which leads to a problem that this verify operation essentially takes long time in comparison with a single operation in which reading is not performed. Further, an operation voltage in the writing/erasing becomes high in comparison with a case of reading, and the writing/erasing may require pre-charging or pre-discharging depending on which reading scheme is used. This causes a further reduction in the speed of the verify operation.
That is, there arises a problem due to the variations of a threshold voltage in the single operation, and there arises a problem due to an operation speed in the verify operation. As a result, performing a high-speed operation with a narrow distribution width of the threshold voltage becomes an important subject in order to improve the performance of a nonvolatile memory.
The present invention has been made in the light of the problems described above. An object of the present invention is to provide a nonvolatile memory that enables high-speed writing/erasing with a narrow distribution width of a threshold voltage. In more detail, an object of the present invention is to provide a verify method that realizes a high-speed operation by shortening a verify operation time and a nonvolatile memory using the verify method. Also, an object of the present invention is to provide a semiconductor device which has such a nonvolatile memory.
A fundamental idea underlying the present invention is that, to realize a high-speed verify operation, there is avoided the repetition of writing/erasing and reading, which has been a factor of consuming a long time in the conventional verify operation. To realize such a verify operation, the most distinguishing feature of the present invention is that writing/erasing and reading are performed at the same time.
The fundamental idea of the verify operation of the present invention is illustrated in the simplified block diagram and the timing chart shown in FIGS. 2 and 4. The block diagram shown in FIG. 2 is the same as the block diagram for the description of the conventional verify operation. In FIG. 2, the reading circuit 202 and the writing/erasing circuit 201 are connected to the selected memory cell 203, and the verify signal Sv outputted from the reading circuit 202 is inputted into the writing/erasing circuit 201. The difference from the conventional verify operation is clearly shown in the timing chart shown in FIG. 4. That is, according to the present invention, writing/erasing and reading are performed at the same time. The verify signal Sv outputted from the reading circuit reflects the state of the memory cell at all times. The verify signal Sv becomes Low in the case where the state of the memory cell differs from a target state, and becomes High in the case where the state of the memory cell coincides with the target state. Also, the writing/erasing circuit refers to Sv at all times and finishes the writing/erasing immediately after the verify signal Sv becomes High.
As described above, the writing/erasing is performed until the polarity of the verify signal Sv is reversed.
As a result, it becomes possible to dramatically shorten a writing/erasing time in comparison with the conventional verify scheme with which writing/erasing and reading are performed in alternate order. In this case, in addition to the effect that the reading time is shortened, there is also obtained an effect that there are shortened a delay time due to variations in potential between writing/erasing and reading and a preparation time required for pre-charging and the like.
In this specification, this scheme will be hereinafter referred to as the xe2x80x9cconstant verify schemexe2x80x9d since reading is constantly performed at all times with the verify scheme described above.
With the constant verify scheme, the writing/erasing and the reading are performed at the same time, therefore it is impossible to apply a conventional reading method as it is. As a result, it is required to use a reading method described below. With the conventional reading method, a judgement is made with reference to whether a memory element is placed in an ON state or in an OFF state and an operation is performed with a low voltage. However, with the reading method applied to the constant verify scheme, it is required to perform reading regardless of whether a memory element is placed in an ON state or in an OFF state. Also, it is required to perform an operation with a high voltage during writing/erasing.
Although it is possible to refer to the following embodiment modes for more detailed information, there frequently occurs a case where a reading accuracy becomes inferior to a case where a judgement is made with reference to whether a memory element is in an ON state or in an OFF state. Accordingly, in the present invention, it becomes important to reduce threshold voltage errors generated during reading. In more detail, it is preferable that the varying degree of a reading amount with respect to a threshold voltage is small and the reading is performed at high speed.
On the other hand, a reading operation performed at a high voltage is preferable because a reading speed is increased. Needless to say, a consumed current is increased in comparison with a case of conventional reading. However, when consideration is given to the fact that writing/erasing is simultaneously performed, the consumed current during the constant verify operation is reduced in comparison with the conventional verify operation.
Here, variations after a verify operation will be described. With the conventional verify operation, it is possible to perform precise reading. However, there exist some elements whose threshold voltages somewhat exceed a target threshold voltage, which determines a distribution width since writing is performed for a certain period. In the present invention, although such variations of a distribution caused due to the above phenomenon do not occur, the reading accuracy is not so high as in the case of the conventional reading method and reading errors determine the distribution width after verify. Accordingly, in the case where the conventional scheme and the constant verify scheme are compared with each other, it is impossible to simply conclude which scheme realizes a narrow distribution width and this depends on which scheme is adopted (the length of a conventional writing period, the reading scheme for the constant verify, and the like). However, in the case where similar distribution widths after verify are obtained, or in the case where a difference of the distribution widths is small enough not to cause any practical problem, the verify scheme of the present invention is superior to the conventional scheme because an operation speed is enormously improved.
There exists no limitation on the structure of the constant verify scheme of the present invention so long as the structure is a verify scheme based on the idea described above. Accordingly, the constant verify scheme of the present invention includes various embodiment modes. Here, an example of the embodiment modes will be simply described and the constant verify scheme will be described using a typical circuit diagram and timing chart. As to detailed embodiments, it is possible to refer to the following embodiment modes and examples.
As embodiments, for instance, it is possible to consider a plurality of structures for each of (1) the type of a memory element, (2) a charge injection/discharge scheme, (3) a reading scheme, (4) a memory cell circuit, and the like.
First, as to the type of a memory element of (1), although there may be a case where a sufficient operation margin is not obtained, it is possible to apply the constant verify scheme to any types of memory elements in principle. For instance, the memory element type may be p-channel type/n-channel type, floating gate structure/MNOS structure/silicon cluster (also called xe2x80x9csilicon dotxe2x80x9d) structure, or a memory transistor on an Si substrate. Also, the memory element may be a memory transistor on an SOI substrate or a memory TFT (thin film transistor) on a substrate with an insulating surface.
As to the charge injection/discharge scheme of (2), it is possible to list injection/discharge scheme using a tunnel current (FN injection/discharge scheme) and an injection scheme using a hot electron (HE injection scheme). It is also possible to apply the constant verify scheme of the present invention to any types of injection/discharge schemes so long as it is possible to simultaneously perform a reading operation.
In the case where the HE injection scheme is used, it is possible to know the state of a memory element by referring to the magnitude of a drain current (or a drain voltage). Also, in the case where the FN injection/discharge scheme is used, it is possible to know the state of a memory element with a drain current (or a drain voltage) by applying an appropriate potential difference between a source and a drain. Also, it is possible to use a method with which reading is performed by judging a tunnel current in principle.
Also, as to the reading scheme of (3), it is possible to use a scheme with which a drain current or a drain voltage is read. Needless to say, another reading scheme may be used. Also, as to the memory cell circuit of (4), it is possible to consider various structures such as NOR type/NAND type or a structure in which one or two elements are included in a memory cell. Aside from these, in connection with the reading scheme and the memory cell circuit, it is possible to classify verify schemes into a scheme based on a bit-by-bit operation and verify and into a scheme based on multiple cell (typically, one line) simultaneous operation and bit-by-bit verify. For more detailed information concerning these structures, it is possible to refer to the following embodiment modes and examples.
Next, the constant verify scheme of the present invention will be described in more detail. FIG. 1 shows an example of a circuit diagram illustrating the verify operation according to the present invention, while FIG. 5 shows an example of a timing chart for the verify operation. In the following description, a source voltage, a drain voltage, and a control gate voltage are referred to as Vs, Vd, and Vcg, respectively. Also, it is assumed that writing/erasing and reading are performed at the same time in the case of (Vd, Vcg)=(Vd1, Vcg1) and writing/erasing is not performed in the case of (Vd, Vcg)=(Vd0, Vcg0). The state and period in the case of (Vd, Vcg)=(Vd1, Vcg1) will be respectively referred to as the xe2x80x9coperation statexe2x80x9d and the xe2x80x9coperation periodxe2x80x9d, while the state and period in the case of (Vd, Vcg)=(Vd0, Vcg0) will be respectively referred to as the xe2x80x9cnon-operation statexe2x80x9d and the xe2x80x9cnon-operation periodxe2x80x9d. Note that Vs remains constant through the operation period and the non-operation period. However, even in a general case where Vs is not constant, it becomes possible to apply the constant verify scheme with an appropriate circuit.
The circuit shown in FIG. 1 includes a selected memory element 101, a sense amplifier 102, a resistor 103, and switches 104 to 108. The source voltage Vs is given to the source region of the memory element 101. Also, the control gate voltage is connected to a word line potential VWL0 or VWL1 via the switch 104. The drain region (whose potential is set to Vd) of time memory element 101 is connected to the resistive element 103 and the remaining terminal of the resistive element 103 is connected to a bit line potential VBL0 or VBL1 via the switch 105. The drain region of the memory element 101 is connected to one of the input terminals (node A) of the sense amplifier 102. The other of the input terminals (node B) of the sense amplifier 102 is connected to a reference voltage Vref0 or Vref1 via the switch 106, and the output from the sense amplifier 102 is connected to a node C via the switches 108 and 107. Also, the potential of the node C is outputted to the outside as the verify signal Sv. The node C is connected to the switches 104, 105, and 106 and performs switching thereof. The switch 108 switches between the output from the sense amplifier 102 and a High signal in accordance with the signal S1, while the switch 107 switches between one terminal of the switch 108 and a Low signal in accordance with the signal S0.
The following description concerns the operations of the switches and sense amplifier constituting the circuit shown in FIG. 1. In the case where the verify signal Sv is High, the switches 104 to 108 are respectively connected to VWL1, VBL1, Vref1, a Low signal, and a High signal. Also, in the case where the verify signal Sv is Low, the switches 104 to 108 are respectively connected to VWL0, VBL0, Vref0, one terminal of the switch 108, and the output from the sense amplifier 102. Also, in the case where the potential of the node A is higher than the potential of the node B, the output from the sense amplifier 102 becomes High. On the other hand, in the case where the potential of the node A is lower than the potential of the node B, the output from the sense amplifier 102 becomes Low.
As a result, the circuit shown in FIG. 1 is placed in an operation state in the case where the verify signal Sv is High, and is placed in a non-operation state in the case where the verify signal Sv is Low. The potential of the verify signal Sv is selected by the signals S0 and S1. In the case where S0 is High and S1 is Low, the verify signal Sv becomes Low. Also, in the case where S0 is Low and S1 is High, the verify signal Sv becomes High. Further, in the case where both of S0 and S1 are Low, the output from the sense amplifier 102 becomes the verify signal Sv.
The sense amplifier 102 compares the drain voltage of the memory element with a reference voltage and outputs a potential in accordance with a relation in magnitude of the voltages. Consequently, in the case where both of S0 and S1 are Low, one of an operation state and a non-operation state is selected in accordance with the output from the sense amplifier 102. As can be seen from this, the circuit shown in FIG. 1 constitutes a feedback circuit in which the verify signal Sv is regarded as a feedback signal.
In the case where the circuit shown in FIG. 1 is regarded as a feedback circuit (S0 and S1 are both Low), each of an operation state and a non-operation state may be in a stable state and an unstable state. The operation state becomes stable in the case where the drain voltage Vd of the memory element is higher than the reference voltage Vref1, and becomes unstable in the case where the drain voltage Vd is lower than the reference voltage Vref1. Also, the non-operation state becomes stable in the case where the drain voltage Vd of the memory element is lower than the reference voltage Vref0, and becomes unstable in the case where the drain voltage Vd is higher than the reference voltage Vref0. In the stable state, the operation state is continued. However, in the unstable state, the shifting to another operation state is performed.
It should be noted here that the resistor 103 is not limited to the resistive element and another circuit may be used so long as the circuit is effectively regarded as a resistor. In addition, although a scheme with which a drain voltage is read is adopted in the circuit shown in FIG. 1, the present invention is not limited to this. A drain current may be read or another publicly known reading method may be applied.
When the circuit described above is used, it becomes possible to perform the constant verify scheme. The following description is explained with reference to the timing chart shown in FIG. 5. The constant verify operation of the present invention is fundamentally constructed of three periods that are (1) a reset period, (2) a first operation period (forced operation period), and (3) a second operation period (constant verify period).
During the reset period of (1), preparations prior to the initiation of a verify operation are conducted. In FIG. 5, S0 is set to a High level and S1 is set to a Low level to obtain a non-operation state. Aside from this, appropriate pre-charging or discharging may be performed in accordance with which operation scheme is used, or the reset period may be omitted.
The first operation period (forced operation period) of (2) is a period in which an operation state is obtained as an initial state of the feedback Circuit shown in FIG. 1. In FIG. 5, there is forcedly obtained an operation state by setting S0 to a Low level and S1 to a High level. The forced operation period is required in the case where a non-operation state is stable in defiance of the threshold voltage of a memory element. In the case of a circuit designed so that the non-operation state becomes unstable if the memory element is not in a target state, the forced operation period may be omitted.
The second operation period (constant verify period) of (3) is a period in which a verify operation is performed in accordance with the feedback circuit. The overwhelming majority of a writing/erasing operation is performed in this period. In FIG. 5, the feedback circuit is constructed by setting both of S0 and S1 as Low signals. The constant verify period is set so that an operation state becomes unstable if the memory element is placed in a target state, and the operation state is shifted to a non-operation sate immediately after the memory element is placed into the target state. Note that it is required that a memory element in the target state is stable in the non-operation state.
FIG. 5 also shows an example in which an operation voltage to be inputted, a threshold voltage, and a drain voltage vary with time. In the following description, there will be considered a verify operation by which the threshold voltage Vth of the memory element is set to a threshold voltage Vthref (Vref1=Vd) or higher in an operation state. Also, there will be considered a case of VBL1 greater than Vref1 greater than VBL0=Vs greater than Vrer0, in which drain voltage is increased in an operation state. The variation with time showing a FIG. 5 is just an example and it is possible to perform a verify operation under a condition of VBL1 less than Vref1 less than VBL0, VBL0 Vs, or Vref0=Vref1. Also, the threshold voltage of a memory element may be decreased or the drain voltage may be decreased in an operation state. In any event, the idea of the constant verify scheme is the same and the differences do not concern the nature of the present invention.
In FIG. 5, in the case where the initial state of the memory element is Vth less than Vthref, a condition of Vd less than Vref1 is obtained during a forced operation, and the operation state becomes stable. The forced operation period is directly shifted to the constant verify period and the operation state is continued until the threshold voltage Vth of the memory element becomes equal to or higher than Vthref. When a condition of Vd Vref1 is obtained, the verify signal Sv is reversed to obtain a non-operation state. That is, the verify operation is finished. The non-operation state is stable because of Vd=VBL0 greater than Vref0. Note that with the verify scheme described above, the initial state after the reset is Vd=VBL0 greater than Vref0 and the non-operation state is stable, and, therefore, the forced operation period is required.
It should be noted here that in the case where the initial state of the memory element is Vth greater than Vthref (shown as Svxe2x80x2, Vthxe2x80x2, and Vdxe2x80x2), a condition of Vdxe2x80x2 greater than Vref1 is obtained during the forced operation, the verify signal Svxe2x80x2 is reversed immediately after the forced operation period is finished, and there is obtained a non-operation. That is, the verify operation is finished. The non-operation state is stable because a condition of Vdxe2x80x2=VBL0 greater than Vref0 is obtained.
In this case, the threshold voltage of a memory element is unnecessarily increased in the forced operation period. Accordingly, it is preferable that the forced operation period is shortened as much as possible. It is preferable that the forced operation period is equal to or shorter than 1 xcexcsec. Since the object of the forced operation period is to read the state of a memory element as the verify signal, it is appropriate that the forced operation period is minimized within a range in which it is possible to accomplish this object. It is possible to perform the reading operation in a very short time period in comparison with the writing/erasing period, therefore it is substantially possible to set the degree of change in a threshold voltage during the forced operation period to a negligible level. Accordingly, there arises no problem due to the unnecessary increase of the threshold voltage in the forced operation period.
In the manner described above, the constant verify operation of the present invention is performed. The above description concerns an example for explaining a typical verify operation and the present invention is not limited to the circuit diagram and the timing chart diagram shown in FIGS. 1 and 5. In general, the fundamental idea is to use a mechanism, in which an operation state is shifted to a non-operation state when a threshold voltage reaches a target state, and therefore any other circuit may be used so long as the circuit has such a mechanism. That is, it is enough to design the circuit so that the operation state becomes stable if the threshold voltage of a memory element is not in the target state and becomes unstable if the threshold voltage of the memory element is in the target state. Also, the circuit may be designed so that the non-operation state becomes unstable if the memory element is not in the target state and becomes stable if the memory element is in the target state. Alternatively, the circuit may be designed so that a stable state is obtained regardless in of the threshold voltage of the memory element.
As described above, according to the present invention, there is realized a verify method with which it is possible to perform high-speed writing/erasing with a narrow distribution width of a threshold voltage. By using such a verify method, there is also realized a nonvolatile memory that is capable of performing high-speed writing/erasing with a narrow distribution width of a threshold voltage. Note that the operation characteristics, such as a high-speed operation and a narrow distribution width of a threshold voltage, are particularly preferable in a multilevel nonvolatile memory.
According to the present invention, that is provided a driving method of a nonvolatile memory, in which during a verify operation, a first operation for changing a threshold voltage of a memory element is performed concurrently with a second operation for judging the threshold voltage of the memory element.
The driving method may be a method, in which at a timing when the threshold voltage of the memory element judged by the second operation becomes a set voltage, the first operation and the second operation are terminated and the verify operation is finished.
According to the present invention, there is provided a driving method of a nonvolatile memory for setting a threshold voltage of a memory element to a set voltage or higher, in which: during a verify operation, a first operation for increasing the threshold voltage of the memory element is performed concurrently with a second operation for judging a relation in magnitude between the threshold voltage of the memory element and the set voltage; a judgement result of the second operation is outputted as a verify signal; the verify signal takes a first value if the threshold voltage of the memory element is smaller than the set voltage, and takes a second value if the threshold voltage of the memory element is larger than the set voltage; the first operation is performed if the verify signal takes the first value; and is not performed if the verify signal takes the second value; and the first operation and the second operation are terminated and the verify operation is finished when the verify signal changes from the first value to the second value.
According to the present invention, there is provided a driving method of a nonvolatile memory for setting a threshold voltage of a memory element to a set voltage or lower, in which: during a verify operation, a first operation for decreasing the threshold voltage of the memory element is performed concurrently with a second operation for judging a relation in magnitude between the threshold voltage of the memory element and the set voltage; a judgement result of the second operation is outputted as a verify signal; the verify signal takes a first value if the threshold voltage of the memory element is larger than the set voltage, and takes a second value if the threshold voltage of the memory element is smaller than the set voltage; the first operation is performed if the verify signal takes the first value, and is not performed if the verify signal takes the second value; and the first operation and the second operation are terminated and the verify operation is finished when the verify signal changes from the first value to the second value.
According to the present invention, there is provided a driving method of a nonvolatile memory for setting a threshold voltage of a memory element to a set voltage or higher, in which: during a verify operation, a first operation for increasing the threshold voltage of the memory element is performed concurrently with a second operation for judging a relation in magnitude between the threshold voltage of the memory element and the set voltage, the verify operation includes at least a first period and a second period that continues from the first period; a verify signal takes a first value during the first period; a judgment result of the second operation is outputted as the verify signal during the second period; during the second period, the verify signal takes the first value if the threshold voltage of the memory element is smaller than the set voltage, and takes a second value if the threshold voltage of the memory element is larger than the set voltage; the first operation is performed if the verify signal takes the first value, and is not performed if the verify signal takes the second value; and the first operation and the second operation are terminated and the verify operation is finished when the verify signal changes from the first value to the second value.
According to the present invention, there is provided a driving method of a nonvolatile memory for setting a threshold voltage of a memory element to a set voltage or lower, in which: during a verify operation, a first operation for decreasing the threshold voltage of the memory element is performed concurrently with a second operation for judging a relation in magnitude between the threshold voltage of the memory element and the set voltage; the verify operation includes at least a first period and a second period that continues from the first period; a verify signal takes a first value during the first period; a judgment result of the second operation is outputted as the verify signal during the second period; during the second period, the verify signal takes the first value if the threshold voltage of the memory element is larger than the set voltage, and takes a second value if the threshold voltage of the memory element is smaller than the set voltage; the first operation is performed if the verify signal takes the first value, and is not performed if the verify signal takes the second value; and the first operation and the second operation are terminated and the verify operation is finished when the verify signal changes from the first value to the second value.
According to the present invention, there is provided a nonvolatile memory that performs a verify operation, including a means for simultaneously performing a first operation for changing a threshold voltage of a memory element and a second operation for judging the threshold voltage of the memory element.
The nonvolatile memory may further include a means for terminating the first operation and the second operation and finishing the verify operation at a timing when the threshold voltage of the memory element judged by the second operation becomes a set voltage.
According to the present invention, there is provide a nonvolatile memory that performs a verify operation for setting a threshold voltage of a memory element to a set voltage or higher, the nonvolatile memory including: a means for simultaneously performing a first operation for increasing the threshold voltage of the memory element and a second operation for judging a relation in magnitude between the threshold voltage of the memory element and the set voltage; a means for, during the second operation, generating a verify signal that takes a first value if the threshold voltage of the memory element is smaller than the set voltage and takes a second value if the threshold voltage of the memory element is larger than the set voltage; a means for performing the first operation if the verify signal takes the first value, and not performing the first operation if the verify signal takes the second value; and a means for terminating the first operation and the second operation and finishing the verify operation, when the verify signal changes from the first value to the second value.
According to the present invention, there is provided a nonvolatile memory that performs a verify operation for setting a threshold voltage of a memory element to a set voltage or lower, the nonvolatile memory including: a means for simultaneously performing a first operation for decreasing the threshold voltage of the memory element and a second operation for judging a relation in magnitude between the threshold voltage of the memory element and the set voltage; a means for, during the second operation, generating a verify signal that takes a first value if the threshold voltage of the memory element is larger than the set voltage and takes a second value if the threshold voltage of the memory element is smaller than the set voltage; a means for performing the first operation if the verify signal takes the first value, and not performing the first operation if the verify signal takes the second value; and a means for terminating the first operation and the second operation and finishing the verify operation when the verify signal changes from the first value to the second value.
According to the present invention, there is provided a nonvolatile memory that performs a verify operation for setting a threshold voltage of a memory element to a set voltage or higher, the nonvolatile memory including: a means for simultaneously performing a first operation for increasing the threshold voltage of the memory element and a second operation for judging a relation in magnitude between the threshold voltage of the memory element and the set voltage; a means for generating a verify signal that takes a first value during a first period; a means for, during a second period that continues from the first period, generating a verify signal that takes the first value if the threshold voltage of the memory element is smaller than the set voltage and takes a second value if the threshold voltage of the memory element is larger than the set voltage; a means for performing the first operation if the verify signal takes the first value, and not performing the first operation if the verify signal takes the second value; and a means for terminating the first operation and the second operation and finishing the verify operation when the verify signal changes from the first value to the second value.
According to the present invention, there is provided a nonvolatile memory that performs a verify operation for setting a threshold voltage of a memory element to a set voltage or lower, the nonvolatile memory including: a means for simultaneously performing a first operation for decreasing the threshold voltage of the memory element and a second operation for judging a relation in magnitude between the threshold voltage of the memory element and the set voltage; a means for generating a verify signal that takes a first value during a first period; a means for, during a second period that continues from the first period, generating a verify signal that takes the first value if the threshold voltage of the memory element is larger than the set voltage and takes a second value if the threshold voltage of the memory clement is smaller than the set voltage; a means for performing the first operation if the verify signal takes the first value, and not performing the first operation if the verify signal takes the second value; and a means for terminating the first operation and the second operation and finishing the verify operation when the verify signal changes from the first value to the second value.
In the nonvolatile memory, the memory element may store multi-state data.